1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Related Art
Recently, semiconductor devices using a silicon on insulator (SOI) substrate have been developed. The SOI substrate is a substrate having a structure in which a buried oxide (BOX) layer (buried oxide film) is buried between a semiconductor substrate and a semiconductor layer (SOI layer). The SOI substrate is used as a substrate of, for example, a NAND type non-volatile semiconductor memory device (refer to JP-A 2006-73939 (KOKAI)).
In a semiconductor device formed using the SOI substrate, a film thickness of a semiconductor layer is optimized based on design items such as an operation frequency, a breakdown voltage, a maximum current value, and the like. For example, in a one side gate MOS static induction transistor (MOS-SIT) structure having a MOS gate on a surface of the SOI substrate, it is possible to make a semiconductor layer thin to improve cut-off characteristics.
However, when it was intended to dispose a contact electrode to a thin semiconductor layer having a thickness of, for example, about several tens of nanometers, a problem arose in that a contact resistance became higher than that when a thick semiconductor layer was used because a contact area (areas of a side surface and a bottom portion of a contact electrode in contact with a semiconductor layer) became insufficient. Further, it was difficult to stably control a depth of the contact electrode in the thin semiconductor layer. Accordingly, when the contact electrode reached a BOX layer formed under the semiconductor layer, a problem arose in that since the bottom portion of the contact electrode could not come into contact with the semiconductor layer, a contact resistance was increased by a further decrease of the contact area. Further, even if the bottom portion of the contact electrode could be formed in the semiconductor layer, since the semiconductor layer was thinned between the bottom portion of the contact electrode and the BOX layer, a problem arose in that the contact resistance was increased.
Further, when it was intended to reduce the contact resistance by causing a material of the contact electrode to react with the semiconductor layer, the semiconductor material was absorbed into the material of the contact electrode. Accordingly, a problem also arose in that partial disconnection occurred between the semiconductor layer and the contact electrode because the semiconductor material became insufficient in the vicinity of the contact electrode.
The following structure is considered to overcome these problems. That is, the structure is a contact structure arranged such that a semiconductor layer is formed after a BOX layer of a contact region is entirely removed, and a bottom portion of a contact electrode is connected to a conductive region disposed on a surface of a semiconductor substrate of the contact region. However, when the BOX layer of the contact region is entirely removed regardless of that a channel region of a transistor includes the semiconductor layer, a step corresponding to a thickness of the BOX layer is formed on the surface of the semiconductor layer and remains as a groove. The groove shape causes a new problem in a subsequent manufacturing process in that a wire is broken or, an unnecessary film buried in a groove is not sufficiently removed in a chemical mechanical polishing (CMP) process and remains, and the like in a wiring step.